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AIC1341
High Performance, Triple-Output, AutoTracking Combo Controller
n FEATURES
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n GENERAL DESCRIPTION
The AIC1341 combines a synchronous voltage mode PWM controller with two linear controllers as well as the monitoring and protection functions in this chip. The PWM controller regulates the output voltage with a synchronous rectified stepdown converter. The built-in N-Channel MOSFET drivers also help to simplify the design of stepdown converter. It is able to power CPUs, GPUs, memories, chipsets and multi-voltage applications. The PWM controller features over current protection using RDS(ON). It improves efficiency and saves cost, as there is no expensive current sense resistor required. Two built-in adjustable linear controllers drive an external MOSFETs to form two linear regulators that regulates power for multiple system I/O. Output voltage of both linear regulators can also be adjusted by means of the external resistor divider. Both linear regulators feature current limit. For a system I/O requires current less than 500mA, the AIC1340 is recommended for saving one external MOSFET. The programmable soft-start design provodes a controlled output voltage rise, which limits the current rate during power on time. The shutdown function is also provided for disabling the combo controller.
Provide Triple Accurate Regulated Voltages Optimized Voltage-Mode PWM Control Dual N-Channel MOSFET Synchronous Drivers Fast Transient Response Adjustable Over Current Protection using RDS(ON). No External Current Sense Resistor Required. Programmable Softstart Function 200KHz Free-Running Oscillator Robust Outputs Auto-Tracking Characteristics Sink and Source Capabilities with External Circuit
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n APPLICATIONS
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Advanced PC Mboards Information PCs Servers and Workstations Internet Appliances PC Add-On Cards DDR Termination
Analog Integrations Corporation 4F, 9, Industry E. 9th Rd, Science Based Industrial Park, Hsinchu Taiwan, ROC DS-1341-00 May 24, 01 TEL: 886-3-5772500 FAX: 886-3-5772510
www.analog.com.tw
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AIC1341
n TYPICAL APPLICATION CIRCUIT
AIC1341CS +12VIN VCC +5VIN 4 14 OCSET UGATE PHASE Q1
+
GND
SS 5 2 1 +3.3VIN VIN2 7 16 10
VOUT1
Q2
LGATE
+
GATE3
VOUT3
+
FB3 11
15
PGND
+3.3VIN FB1 13 GATE2 8
VOUT2
+
FB2 6
12 COMP1 14 GND 3 SD
Typical Triple-Output Application
n ORDERING INFORMATION
AIC1341-XX
PACKAGING TYPE S: SMALL OUTLINE TEMPERATURE RANGE C: O C~+70C
ORDER NUMBER
AIC1341CS (SO 16)
PIN CONFIGURATION
PHASE 1 16 LGATE 15 PGND 14 OCSET 13 F B 1 12 COMP1 11 F B 3 10 GATE3 9 GND
UGATE 2 SD VCC 3 4
SS 5 FB2 6 VIN2 GATE2 7 8
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AIC1341
n ABSOLUTE MAXIMUM RATING
Absolute Maximum Ratings Supply Voltage (VCC).............................................................................................................. 15V UGATE....................................................................................................GND - 0.3V to VCC + 0.3V LGATE ....................................................................................................GND - 0.3V to VCC + 0.3V Input Output and I/O Voltage .................................................................................GND - 0.3V to 7V Operating Conditions Ambient Temperature Range ........................................................................................ 0 C to 85C Maximum Operating Junction Temperature ............................................................................. 100C Supply Voltage, VCC....................................................................................................... 15V10% Thermal Information Thermal Resistance JA (C/W) SOIC Package ....................................................................................................... 100C/W Maximum Junction Temperature (Plastic Package).................................................................. 150C Maximum Storage Temperature Range.......................................................................-65C to 150C Maximum Lead Temperature (Soldering 10s)........................................................................... 300C
n TEST CIRCUIT
Refer to APPLICATION CIRCUIT.
n ELECTRICAL CHARACTERISTICS
specified)
PARAMETER VCC SUPPLY CURRENT Supply Current TEST CONDITIONS
(Vcc=12V, T J=25C, Unless otherwise
SYMBOL
MIN.
TYP.
MAX.
UNIT
UGATE, LGATE, GATE2 and GATE3 open
ICC
1.8
5
mA
POWER ON RESET Rising VCC Threshold Falling VCC Threshold Rising VIN2 Under-Voltage Threshold VIN2 Under-Voltage Hysteresis Rising VOCSET1 Threshold VOCSET=4.5V VOCSET=4.5V VCCTHR VCCTHF VIN2THR VIN2HYS VOCSETH 8.6 8.2 2.5 9.5 9.2 2.6 10.4 10.2 2.7 V V V
130
mV
1.3
V
3
AIC1341
n ELECTRICAL CHARACTERISTICS
PARAMETER OSCILLATOR and REFERENCE Free Running Frequency FB2 Reference Voltage FB3 Reference Voltage LINEAR CONTROLLER Regulation Under-Voltage Level 0 < IGATE2/3 < 10mA FB2/3 falling TEST CONDITIONS
(Continued)
SYMBOL
MIN.
TYP.
MAX.
UNIT
F VREF2 VREF3
170 1.245 1.250
200 1.270 1.275
230 1.295 1.300
KHz V V
-2.5 FB2/3UV 70
+2.5 80
% %
PWM CONTROLLER ERROR AMPLIFIER DC GAIN Gain Bandwidth Product Slew Rate COMP1=10pF GBWP SR 76 11 6 dB MHz V/S
PWM CONTROLLER GATE DRIVER Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink PROTECTION Soft-Start Current Chip Shutdown Soft Start Threshold ISS 11 1.0 A V VCC=12V, VUGATE=11V VCC=12V, VUGATE =1V VCC=12V, VLGATE=11V VCC=12V, VLGATE=1V RUGH RUGL RLGH RLGL 5.2 3.3 4.1 3 6.5 5 6 5
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AIC1341
n PIN DESCRIPTIONS
Pin 1: PHASE: Over-current detection pin. Connect the PHASE pin to source of the external high-side NMOSFET. This pin detects the voltage drop across the high-side N-MOSFET RDS(ON) for overcurrent protection. UGATE: External high-side N-MOSFET gate drive pin. Connect UGATE to gate of the external high-side N-MOSFET. SD: To shut down the system, active high or floating. If connecting a resistor to ground, keep the resistor less than 4.7K[ The chip power supply pin. It also provides the gate bias charge for all the MOSFETs controlled by the IC. Recommended supply voltage is 12V. Soft-start pin. Connect a capacitor from this pin to ground. This capacitor, along with an internal 10A (typically) current source, sets the soft-start interval of the converter. Pulling this pin low will shut down the IC. Connect this pin to a resistor d ivider to set the linear regulator output voltage. This pin supplies power to the internal regulator. Connect this pin to a suitable 3.3V source. Additionally, this pin is used to monitor the 3.3V supply. If, following a start-up cycle, the voltage drops below 2.6V (typically), the chip shuts down. A new softstart cycle is initiated upon r e turn of the 3.3V supply above the under-voltage threshold. Pin 8: GATE2: Linear Controller output drive pin. This pin can drive either a Darlington NPN transistor or a Nchannel MOSFET. GND: Signal GND for IC. All voltage levels are measured with respect to this pin.
Pin 9:
Pin 2:
Pin 3:
Pin 10: GATE3: Linear Controller output drive pin. This pin can drive either a Darlington NPN transistor or an Nchannel MOSFET. Pin 11: FB3 Negative feedback pin for the linear controller error amplifier connect this pin to a resistor divider to set the linear controller output voltage.
Pin 4:
VCC:
Pin 5:
SS:
Pin 12: COMP1 External compensation pin. This pin is connected to error amplifier output and PWM comparator. A RC network is connected to FB1 to compensate the voltage control feedback loop of the converter. Pin 13: FB1 The error amplifier inverting input pin. The FB1 pin and COMP1 pin are used to compensate the voltage-control feedback loop.
Pin 6:
FB2:
Pin 7:
VIN2:
Pin 14: OCSET: Current limit sense pin. Connect a resistor R OCSET from this pin to the drain of the external high-side N-MOSFET. ROCSET, an internal 200A current source (IOCSET ), and the upper N-MOSFET onresistance (RDS(ON)) set the overcurrent trip point according to the following equation:
I PEAK =
I OCSET x ROCSET RDS(ON)
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AIC1341
Pin 15: PGND: Driver power GND pin. PGND should be connected to a low impedance ground plane in close to lower N-MOSFET source. Pin 16: LGATE: Lower N-MOSFET gate drive pin.
n TYPICAL PERFORMANCE CHARACTERISTICS
UGATE
UGATE
LGATE
LGATE
Fig.1 The gate drive waveforms
FAULT
SS
VOUT1 =3.5V
SS
VOUT1 =2V
Over Load Applied Inductor Current 10A/div
VOUT1 =1.3V
Fig.2 Over-Current Operation on Inductor
Fig.3 Soft start initiates PWM Output
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AIC1341
n TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
VOUT1
VOUT3 ( 2mV/div)
2.0VDC
5A to 12A Load Step
1A to 2A Load Step
Fig.4 Transient Response of PWM Output
Fig.5 Transient Response of Linear Controller
n BLOCK DIAGRAM
VIN2 VCC
SS
FB3
+ + 9.5V
+ 1.3V 200uA
OCSET
GATE3 + 0.3V + + GATE2 1.26V
SS
LUV + 2.6V
POR FB2 INHIBIT OC1 + PHASE VCC
COUNT 3 LUV OC1 R
S R
Q
UGATE
3.6V
+
S R
Q
+
POR
GATE CONTROL
5V
S 0.2V + R
Q
PWM COMP VCC SS 200KHz OSCILLATOR LGATE PGND
10uA SS
SLOW DISCHARGE 4V 20uA 5V 70K FAST DISCHARGE 1.3V
+
ERROR AMP
GND
SD
FB1
COMP1
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AIC1341
n DESCRIPTION
The AIC1341 is designed for applications with multiple voltage demand. This IC has one PWM controller and two linear controllers. The PWM controller is designed to regulate the voltage (V OUT1) by driving 2 MOSFETs ( y UGATE and B LGATE) in a synchronous rectified buck converter configuration. The voltage is regulated to a level, which is decided by a resistor devide network. The Power-On Reset (POR) function continually monitors the input supply voltage +12V at VCC pin, the 5V input voltage at OCSET pin, and the 3.3V input at VIN2 pin. The POR function initiates soft-start operation after all three input supply voltage exceeds their POR thresholds. Soft-Start The POR function initiates the soft-start sequence. Initially, the voltage on SS pin rapidly increases to approximate 1V. Then an internal 10A current source charges an external capacitor (CSS) on the SS pin to 4V. As the SS pin voltage slews from 1V to 4V, the PWM error amplifier reference input (Non-inverting terminal) and output (COMP1 pin) is clamped to a level proportional to the SS pin voltage. As the SS pin voltage slew from 1V to 4V, the output clamp generates PHASE pulses of increasing width that charge the output capacitors. Additionally both linear regulator's reference inputs are clamped to a voltage proportional to the SS pin voltage. This method provides a controlled output voltage smooth rise. Fig.3 shows the soft-start sequence for the typical application. The internal oscillator's triangular waveform is compared to the clamped error amplifier output voltage. As the SS pin voltage increases, the pulse width on PHASE pin increases. The interval of increasing pulse width continues until output reaches sufficient voltage to transfer control to the input reference clamp. Each linear output (V OUT2 and VOUT3) initially follows a ramp. When each output reaches sufficient voltage the input reference clamp slows the rate of output voltage rise. Over-Current Protection All outputs are protected against excessive overcurrent. The PWM controller uses upper MOSFET's on-resistance, RDS(ON) to monitor the current for protection against shorted outputs. Both the linear regulator and controller monitor FB2 and FB3 for under-voltage to protect against excessive current. When the voltage across Q1 (ID E RDS(ON)) exceeds the level (200AEROCSET ), this signal inhibit all outputs. Discharge soft-start capacitor (Css) with 10A current sink, and increments the counter. Css recharges and initiates a soft-start cycle again until the counter increments to 3. This sets the fault latch to disable all outputs. Fig. 2 illustrates the over-current protection until an over load on OUT1. Should excessive current cause FB2 or FB3 to fall below the linear under-voltage threshold, the LUV signal sets the over-current latch if Css is fully charged. Cycling the bias input power off then on reset the counter and the fault latch. The over-current function for PWM controller will trip at a peak inductor current (IPEAK) determined by:
IPEAK =
IOCSET x R OCSET R DS(ON)
The OC trip point varies with MOSFET's temperature. To avoid over-current tripping in the normal operating load range, determine the R OCSET resistor from the equation above with: 1. The maximum RDS(ON) at the highest junction. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK > IOUT(MAX) + (inductor ripple current) /2.
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AIC1341
Shutdown Compatible with the TTL logic level, by holding the SD (pin3) pin low will activate the controller. If connecting a resistor to ground, make sure the resistor is less than 4.7K for normal operation. Q1, Q2 loop. The GND and PGND pins should be shorted right at the IC. This help to minimize internal ground disturbances in the IC and prevents differences in ground potential from disrupting internal circuit operation. 5) The wiring traces from the control IC to the Layout Considerations Any inductance in the switched current path generates a large voltage spike during the switching interval. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. Careful component selection and tight layout of critical components, and short, wide metal trace minimize the voltage spike. 1) A ground plane should be used. Locate the input capacitors (CIN) close to the power switches. Minimize the loop formed by C , IN the upper MOSFET (Q1) and the lower MOSFET (Q2) as possible. Connections should be as wide as short as possible to minimize loop inductance. 2) The connection between Q1, Q2 and output inductor should be as wide as short as practical. Since this connection has fast voltage transitions will easily induce EMI. 3) The output capacitor (COUT ) should be located as close the load as possible. Because minimize the transient load magnitude for high slew rate requires low inductance and resistance in circuit board 4) The AIC1341 is best placed over a quiet ground plane area. The GND pin should be connected to the groundside of the output capacitors. Under no circumstances should GND be returned to a ground inside the C , IN PWM Output Capacitors The load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demand. The ESR (equivalent series resistance) and ESL (equivalent series inductance) parameters rather than actual capacitance determine the buck c apacitor values. For a given transient load magnitude, the output voltage transient change due to the output capacitor can be note by the following equation: A multi-layer printed circuit board is recommended. Figure 6 shows the connections of the critical components in the converter. The CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. MOSFET gate and source should be sized to carry 1A current. Locate C OUT2 close to the AIC1341 IC. 6) The Vcc pin should be decoupled directly to GND by a 1F ceramic capacitor, trace lengths should be as short as possible.
VOUT = ESR x IOUT + ESL x
IOUT is transient load current step.
IOUT , T
where
9
AIC1341
+
+12V
VCC +3.3VIN + Q3 VOUT3 + COUT3 GATE3 VIN2
GND OCSET
+5VIN
UGATE Q1 PHASE
+ C IN
LOUT + LGATE Q2
VOUT
COUT
Q4
GATE2 SS
PGND
V OUT2 + COUT2
Css
Power Plane Layer Circuit Plane Layer Via Connection to Ground Plane
Fig.6 Printed circuit board power planes and islands
After the initial transient, the ESL dependent term drops off. Because the strong relationship between output capacitor ESR and output load transient, the output capacitor is usually chosen for ESR, not for capacitance value. A capacitor with suitable ESR will usually have a larger capacitance value than is needed for energy storage.
The response time to a transient is different for the application of load and remove of load.
L x IOUT L x IOUT , tFALL = . VIN - VOUT VOUT Where IOUT is transient load current step. tRISE =
In a typical 5V input, 2V output application, a 3H A common way to lower ESR and raise ripple current capability is to parallel several capacitors. In most case, multiple electrolytic capacitors of small case size are better than a single large case capacitor. Output Inductor Selection Inductor value and type should be chosen based on output slew rate requirement, output ripple r equirement and expected peak current. Inductor value is primarily controlled by the required current response time. The AIC1341 will provide either 0% or 85% duty cycle in response to a load transient. inductor has a 1A/S rise time, resulting in a 5S delay in responding to a 5A load current step. To optimize performance, different combinations of input and output voltage and expected loads may require different inductor value. A smaller value of inductor will improve the transient response at the expense of increase output ripple voltage and inductor core saturation rating. Peak current in the inductor will be equal to the maximum output load current plus half of inductor ripple current. The ripple current is approximately equal to:
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AIC1341
(V IN - VOUT) x VOUT ; f x L x VIN
dissipated by the AIC1341. However, the gate charge increases the switching interval, tSW, which increase the upper MOSFET switching losses. Ensure that both MOSFETs are within their The inductor must be able to withstand peak current without saturation, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications.
I RIPPLE =
f = 200KHz oscillator frequency.
PUPPER = IOUT 2 x RDS(ON) x D +
Input Capacitor Selection Most of the input supply current is supplied by the input bypass capacitor, the resulting RMS current flow in the input capacitor will heat it up. Use a mix of input bulk capacitors to control the voltage overshoot across the upper MOSFET. The ceramic capacitance for the high frequency decoupling should be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedance. The buck capacitors to supply the RMS current is approximate equal to:
PLOWER = IOUT 2
IOUT x VIN x tSW x f 2 x RDS(ON) x (1 - D)
The equations above do not model power loss due to the reverse recovery of the lower MOSFET's body diode. The RDS(ON) is different for the two previous equations even if the type devices is used for both. This is because the gate drive applied to the upper MOSFET is different than the lower MOSFET. Logic level MOSFETs should be selected based on on-resistance considerations, RDS(ON) should be chosen base on input and output voltage, a l-
IRMS = (1- D) x D x I2 OUT +
, where D =
1 VIN x D x 12 f x L
2
lowable power dissipation and maximum required output current. Power dissipation should be calculated based primarily on required efficiency or allowable thermal dissipation. Rectifier Schottky diode is a clamp that prevent the loss parasitic MOSFET body diode from conducting during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. The diode's rated reverse breakdown voltage must be greater than twice the maximum input voltage. Linear Controller MOSFET Selection The power dissipated in a linear regulator is :
VOUT VIN
The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage.
PWM MOSFET Selection In high current PWM application, the MOSFET power dissipation, package type and heatsink are the dominant design factors. The conduction loss is the only component of power dissipation for the lower MOSFET, since it turns on into near zero voltage. The upper MOSFET has conduction loss and switching loss. The gate charge losses are proportional to the switching frequency and are
PLINEAR = IOUT x (VIN2 - VOUT)
Select a package and heatsink that maintains junction temperature below the maximum rating
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AIC1341
while operation at the highest expected ambient temperature. Linear Output Capacitor The output capacitors for the linear controller provide dynamic load current. The linear controller uses dominant pole compensation integrated in the error amplifier and is insensitive to output capacitor selection. C eOUT2 and C OUT3 should be s lected for transient load regulation. Notes VOUT1 - The PWM output VOUT2 - The linear controller dominated by FB2, GATE2 and VIN2 VOUT3 - The linear controller dominated by FB3 and GATE3 All the designators mentioned above are refering to the TYPICAL APPLICATION CIRCUIT in previous page.
12
AIC1341
n APPLICATION CIRCUIT
AIC1341CS 10 VCC 4 14 1000pF K 2K OCSET UGATE PHASE 7 H 16 GATE3 FB3 11 3.3V 10 PGND LGATE 6030L 6030L 0.1 F 1 H +5VIN +12VIN
+
1000F*2 GND
1 F
SS 5 0.1F 1 2
5V OUT
+5.0VIN VIN2 6030L 7
+
1000 F *5
VOUT3
15
+
3.9K 2.4K
+5.0VIN FB1 13 6030L VOUT2 2.5V 2.4K 2.4K 14 GND 3 SD 12 COMP1 1000pF GATE2 8 FB2 6 33pF 91K
24K
8.2K
+
Circuit 1 Multiple Voltage Power application Circuit
13
AIC1341
n PACKAGE DIMENSIONS
l 16 LEAD PLASTIC SO (300 mil) (unit: mm)
D
SYMBOL A A1
E H
MIN 2.35 0.10 0.33 0.23 10.10 7.40 10.00 0.40
MAX 2.65 0.30 0.51 0.32 10.50 7.60 1.27(TYP) 10.65 1.27
B C D E e
e A
H
A1 B c L
L
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